(1) Field of the Invention
The present invention relates to the manufacture of integrated circuits in general, and more particularly to a method of forming a self-aligned poly as a source line in a memory array.
(2) Description of the Related Art
Self-alignment techniques are important in VLSI and ULSI (very large and ultra large scaled integrated) fabrication technology since they reduce the difficulties of precise alignment, and allow considerable shrinkage of the device size. A measure of the degree of shrinkage in each new generation of technology is the minimum gate length, for example, in MOS (metal-oxide-semiconductor) devices. At the same time, it is known that in order to assure proper MOS device operation, it is essential to have an overlap between the gate and the source/drain electrodes of the device in mask alignment during device fabrication. The overlap, on the other hand, is governed by the gate length. Thus, source and drain regions might not line up correctly relative to the gate, deposited contacts might not line up perfectly inside contact holes. It is disclosed later in the embodiments of the present invention a method of forming a self-aligned source to an adjacent transistor and a self-aligned contact.
In prior art, a variety of techniques have been introduced to overcome these problems. In U.S. Pat. No. 5,710,073, Jeng, et al., use a configuration of spacers and etch barriers to form self aligned source and drain contacts. Antireflective silicon nitride cap layers and highly selective etches are used to define smaller interconnect openings. First spacers are formed on the gate electrodes. Later, the second spacers are formed in insulation layers over the gate electrodes. The self-aligning process, which uses the two set of spacers, allows a wide processing window for contact etching to form the contact hole and permit a small contact aspect ratio. The method reduces the masking steps by defining both the source and drain contacts in the same masking step.
A different method of manufacturing self-aligned bit-line is proposed by Sung, et al., in U.S. Pat. No. 5,589,413 where an electrically programmable read only memory device is provided with self-aligned bit-lines in a semiconductor substrate. A tunnel oxide layer is formed on the substrate. Blanket layers of doped, polysilicon layer, an interelectrode dielectric layer and a blanket polycide layer are formed over the dielectric layer. Another dielectric layer is formed over the blanket polycide layer and a silicon nitride layer. A self-aligned source and drain etching process forms gate electrode stacks with trench spaces between the stacks in an array. Spacer dielectric structures are formed adjacent to the sidewalls over the drain regions leaving narrow drain spaces therebetween and spacer dielectric plugs completely filing the spaces over the source regions. A blanket dielectric layer is formed over the stacks, spaces and sidewalls. Drain bit-line openings are etched to the drain regions through the blanket dielectric layer and the tunnel oxide layer over the drain regions between the spacers. A barrier metal layer is formed over the drain regions. A conductive metal layer in contact with the drain regions through the bit-line openings is etched to form the metal layer leaving the bit-lines across the device and contacting with the drain regions.
Chang, et al., in U.S. Pat. No. 5,817,562 teach a method for making more reliable self-aligned contacts (SAC) with improved sidewall profiles. The method uses a stacked gate electrode layer having a TEOS oxide and a hard mask of silicon nitride on the gate electrode polysilicon layer. During patterning of the stacked gate electrode structure using a photoresist mask, the hard mask minimizes the buildup of a polymer on the TEOS oxide sidewall. This results in improved gate electrode line length tolerance and much improved sidewall spacers that minimize electrical shorts between the metal source/drain contact and the polysilicon gate electrodes.
Huang of U.S. Pat. No. 5,863,820 proposes integrating the self-aligned contact process with salicide process on a chip wherein logic and memory share the same chip. Contacts to the memory circuits are made using the SAC process, thus ensuring maximum density, while the logic circuits are made using SALICIDE process, thus ensuring high performance. The two process are integrated within a single chip by first forming polysilicon gate pedestals, those located in the memory areas also having hard masks of silicon nitride. Next, spacers are grown on the vertical sides of the pedestals. Source/drain regions are formed, and then the pedestals on the memory side are given a protective coating of oxide. This allows SALICIDE processes to be selectively applied to only the logic side. Then, while the logic side is protected, the SAC process is applied to the memory side.
In the prior art cited above, the source line that runs continuously between memory cells in an array within the substrate must have sufficient contact size which in turn must have proper spacing to the poly lines for shorts not to occur. This is shown in a top view of substrate (10) in FIG. 1a, where field oxide regions (20) are formed defining source regions (30). Buried source line (50) runs across the source regions in the memory array. The word lines (40) are formed over the substrate and are separated by width w1=2.times.d1+d2, where d1 is the distance from the field oxide to the source line, and d2 is the width of the source line. This is to be compared with the proposed structure shown in FIG. 1b, where poly line (60) of width w2=d3 forms the source line connecting source regions (20) which are isolated from one another by isolation regions (20). It will be disclosed later in the embodiments of the instant invention that the poly source line is formed with a narrow spacer (65) with an oxide cap over the floating gate such that separation of d1 is no longer needed. It will be apparent to those skilled in the art that the isolation regions can be continuous without providing the d1 distance required, and, therefore, width w2=d3 can be made much smaller than w1=2.times.d1+d2. Thus, the disclosed method of forming source line provides a much smaller cell size.